The present disclosure relates to a programmable logic controller (PLC) system, and more particularly, to data processing apparatus and method in the PLC system.
In a PLC system using a micro processing unit (MPU) with limited input and output (I/O) ports, when I/O points get increased, the I/O ports may be expanded by using flip-flops and buffers having an information storing function. At this time, data and clock signals or enable signals are applied to the flip-flops and the buffers. In case of expanding the output ports, data and clock signals are applied to the flip-flops. The clock signals may be generated by combining a write (WR) signal and a chip select (CS) signal by using a logic circuit. In order to increase ability of the logic circuit to withstand a noise, bypass capacitors may be added for bypassing the noise.
This circuit design type may cause a signal delay due to the capacitors and the logic circuit. In addition, not data desired to be output to a data bus, but next data or data in a transition process may be output.
FIG. 1 is an operation flowchart of a related art PLC program, and FIG. 2 is a timing diagram according to a related art clock signal.
Referring to FIGS. 1 and 2, an MPU first performs an initial operation in an operation mode of a PLC system (operation S10).
The MPU collects input data to be used in performing the operation mode using the PLC program and performs an input image area refresh operation that the collected data is stored in the input image area (operation S20).
The MPU may perform the operation mode on the basis of a preset program, and store data input according to the performance of the program in the input image area. Here, an operation result may be updated in the input image area in real time (operation s30).
The MPU may perform an output image area refresh operation that data stored in an output image area according to performance of the program are sent to an output port or an output buffer (operation s40).
As described above, when data stored in the output image area is sent to the output port or the output buffer, a chip select 1 (CS1) signal, which is an address specifying signal corresponding to a buffer as shown in FIG. 2, and a WR signal transit to a low level and a clock signal output from an OR gate also transits to a low level. Due to an effect by the added capacitors to the logic circuit, like a reference numeral 210, delays 210a and 210b may occur between falling and rising times of the clock signal and falling and rising times of the WR signal. Accordingly, data 220 updated to an output Q may not be valid according to the occurrence of the delays.
That is, although a clock speed of the MPU increases, capacitors used to increase ability to withstand a noise and logic gates for clock signal generation cause signal delays. Thus, errors may occur between valid data desired to be output and actually output data.